The present invention relates to the field of sensing amplifiers in semiconductor memory devices, and more particularly to a sensing amplifier for read only memory devices or the like which employ NAND type cells as storage elements.
The prior art regarding the sensing amplifier for memory devices will be described with reference in FIG. 1 to FIG. 5.
As shown in FIG. 1, a conventional formation of NAND type cells was composed of a large number of MOSFET's. The first MOSFET which the gate thereof connected to a selection line and the drain thereof connected to a column line has been utilized as a cell for selecting a cell string, the others which each gate thereof connected to one of the row lines 1 to N in order to select a cell, each drain thereof connected to a source of one adjoined cell and each source thereof connected to a drain of the other adjoined cell forming into a serial cell string have been utilized as unit storage elements.
In the NAND type cells, a cell as a unit storage element was able to have a positive threshold voltage of approximately a range of 0.5 volts to 2.0 volts or a negative threshold voltage of approximately not more than -0.5 volts, and a low level voltage of approximately zero volts was applied to the gate of selected unit storage element, on the contrary, high level voltage of approximately 5 volts was applied to the gate of unselected unit storage element. Therefore, the column line became an electric charged state or an electric discharged state in accordance with the states of cells.
Generally, the sensing amplifier of the prior art having two inputs connected to a column line and a reference line respectively has sensed the state of selected NAND type cells by amplifying the potential difference between two inputs, wherein the reference line had a potential approximately equal to the middle potential between charged state potential and discharged state potential of the column line.
FIG. 2 is a block diagram for explaining a memory device having a cell sensing amplifier of the prior art. As shown in FIG. 2, to maintain the uniform potential of the reference line which was approximately equal to the middle potential between the two states of the column line, dummy cells C1' to Cn' which are the same as the cells C1 to Cn connected to the column line were connected to the reference line. And, to maintain the uniform charged potential or discharged potential of the column line, each of the column line and the reference line was independently connected to a biasing circuit composed of the same number of MOSFET's, in which the first MOSFET group was coupled to the column line connected to the non-inverting input of an amplifier, and the second MOSFET group was coupled to the reference line connected to the inverting input of the amplifier. Therefore, the column line and the reference line had got the same immunity over against outer noise and process change, thus the state of the cells was fully sensed although small voltage difference was merely occurred on the column line in contrast with the reference line. This type of sensing amplifier is disclosed in U.S. Pat. No. 4,223,394.
Also, another type, in which dummy cells connected to the reference line are different from the cells connected to the column line, has been utilized in order to make the reference load.
FIG. 3 is a schematic circuit diagram for illustrating an improved sensing amplifier of the recent prior art. In FIG. 3, a reference numeral 101 denotes a cell string selecting part, 102 a memory part, 103 a reference cell string selecting part, 104 a reference cell part, 105 an added reference cell part, 106 and 107 preamplifying parts, 108 an equalizing part, and 109 denotes an amplifying part, respectively.
According to the increasing memory cells in large scale integrated memory device, the delay time of row lines was seriously increased. So, the memory device of the recent prior art as shown in FIG. 3, employed the NAND type cells and a sensing amplifier for rapid sensing the state of memory cells. The memory device was composed of a cell string selecting part 101 connected to the column line and to selection lines 1 to N, a memory part 102 connected to row lines 1 to N and to the cell string selecting part 101, a reference cell string selecting part 103 connected to the reference line and to the selection lines 1 to N, a reference cell part 104 connected to the row lines 1 to N and to the reference cell string selecting part 103, an added reference cell part 105 connected to the reference line, a preamplifying part 106 connected to the column line, a preamplifying part 107 connected to the reference line, an equalizing part 108 connected to the column line and to the reference line, and an amplifying part 109 connected to the two preamplifying parts 106 and 107.
The cell string selecting part 101 was composed of a large number of MOSFET's(n) of which each drain was connected to the column line, and each gate was connected to one of the selection lines 1 to N. The memory part 102 was composed of a very large number of MOSFET's(n.times.n) forming a large number of cell strings(n) in which respective drains of the first MOSFET's were connected to the respective sources of MOSFET's in the cell string selecting part 101, respective gates of MOSFET's(n.times.n) were connected to the row lines 1 to N respectively in order to select the cells each cell string, and the sources and drains of adjoined MOSFET's were connected to each other in order to form the serial cell strings. The reference cell string selecting part 103 was composed of a large number of MOSFET's(n) of which each drain was connected to the reference line, and each gate was connected to one of the selection lines 1 to N. The reference cell part 104 was composed of a very large number of MOSFET's(n.times.n) forming a large number of reference cell strings(n) wherein respective drains of the respective first MOSFET's were connected to the respective sources of MOSFET's in the reference cell string selecting part 103, respective gates of all MOSFET's(n.times.n) were connected to the row lines 1 to N respectively in order to select the cells each reference cell string, and the sources and drains of adjoined MOSFET's were connected to each other in order to form the serial reference cell strings. The added reference cell part 105 was composed of a large number of MOSFET's in which a drain of first MOSFET was connected to the reference line, and the other sources and drains of the MOSFET's were mutually connected to the adjoined MOSFET's in order to form a serial cell string, which performs a function of applying to the reference line a uniform potential. The first preamplifying part 106 was connected to the column line, which performs a function of preamplifying the applied potential of the column line. The second preamplifying part 107 was connected to the reference line, which performs a function of preamplifying the applied potential of the reference line in order to make the applied potential into a standard potential. The equalizing part 108 was connected to the column line and to the reference line, which performs a function of equalizing the two lines. The amplifying part 109 was respectively connected to the first and the second preamplifying parts 106 and 107, which performs a function of operational amplifying the difference of the preamplified potentials between two inputs.
That is to say, in the memory device having NAND type cells, the cells of the reference cell string selecting part 103 and the reference cell part 104 which were arranged in the same formation as the cells connected the column line in order to get the same immunity, and another cell string 105 was further added to the reference line in order to get the uniform potential.
FIG. 4 and FIG. 5 are timing diagrams showing a plot of voltage vs. time for nodes in the circuit of FIG. 3. In FIG. 4 and FIG. 5, a reference mark PRE denotes a precharging signal applied to the first and the second preamplifying parts 106 and 107, an EQ denotes an equalizing signal applied for the equalizing part 108, a SAOUT denotes an output signal from the amplifying part 109, and a t1 denotes a duration from an address inputting time to an output signal outputting time, wherein the outputting time is the time when the output signal is just coming out from the amplifying part 109, respectively.
Now, referring to FIG. 4, there is shown a timing diagram in the case that the selected unit storage element connected to the column line had a positive threshold voltage of approximately 0.5 to 2.0 volts, wherein the signals of the column line and the reference line were started separating each other from the time when the equalizing signal EQ was just turned into low level.
Referring to FIG. 5, there is shown another timing diagram in the case that the selected unit storage element connected to the column line had a negative threshold voltage not more than -0.5 volts. In this case, on the other hand the signal of the column line was gradually rising, the signal of the reference line was gradually falling for a little, while after the equalizing signal EQ was just turned into low level, for that reason, the signal of the column line had higher potential than the signal of the reference line for a little while. And then, according to elapsing of time, the signal of the column line was gradually falling and the signal of the reference line was gradually rising, at last the signals were normally separated.
Exactly, after the equalizing signal EQ was just turned into low level, the current flowing through the reference line was about the same as a sum of the current flowing on the reference load and the current flowing on the cell connected to the reference line, in order that the cell could be changed from turn-on state to turn-off state according as the potential of selected column line was changed into zero volts from 5 volts and the potential of unselected column line was changed into 5 volts from zero volts. At this time the current flowing through the column line was the about same as only current flowing on the selected cell which was changing from turn-off state to turn-on state. So, the current flowing through the reference line was bigger than the current flowing through the column line until the cell connected to the reference line turned-off, and the potential of the column line was higher than the potential of the reference line for a little while, and then, according to elapsing of time the potentials were gradually separating into normal potentials for the column line and reference line.
Therefore, the sensing amplifier for memory devices having NAND type cells of the prior art had problems that, as shown in FIG. 5, an error was occurred on the output signal of the cell sensing amplifier for a while, and sensing speed was badly delayed because the transition period had existed until the output was perfectly stabilized.